// Copyright (C) 1953-2022 NUDT
// Verilog module name - command_parse_inex 
// Version: V3.4.0.20220228
// Created:
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module command_parse_inex
(
       i_clk,
       i_rst_n,
       
       iv_command,
	   i_command_wr,    
       
       ov_hcp_int_command  ,
	   o_hcp_int_command_wr,

       ov_hcp_ext_command  ,
       o_hcp_ext_command_wr   
);


// I/O
// i_clk & rst
input                  i_clk;
input                  i_rst_n;      
//nmac data
input      [65:0]      iv_command;               // input nmac data
input                  i_command_wr;             // nmac writer signals

output reg [65:0]	   ov_hcp_int_command   ;
output reg	           o_hcp_int_command_wr ;

output reg [65:0]	   ov_hcp_ext_command   ;
output reg	           o_hcp_ext_command_wr ;
//////////////////////////////////////////////////
//                  state                       //
//////////////////////////////////////////////////
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        ov_hcp_int_command         <= 66'b0;
        o_hcp_int_command_wr       <= 1'b0 ;
		
		ov_hcp_ext_command             <= 66'b0;
        o_hcp_ext_command_wr           <= 1'b0 ;        
    end
    else begin
        if(i_command_wr)begin//hcp
            if(iv_command[63:62] == 2'b00)begin    
                ov_hcp_int_command         <= iv_command;//{iv_command[65:64],iv_command[61:0]};
                o_hcp_int_command_wr       <= 1'b1;  
                
                ov_hcp_ext_command             <= 66'b0;
                o_hcp_ext_command_wr           <= 1'b0;
            end
            else begin//tss or tse
                ov_hcp_int_command         <= 66'b0;
                o_hcp_int_command_wr       <= 1'b0;
                
                ov_hcp_ext_command             <= iv_command;//{iv_command[65:64],iv_command[61:0]};
                o_hcp_ext_command_wr           <= 1'b1;	
            end           
        end 
        else begin
            ov_hcp_int_command             <= 66'b0;
            o_hcp_int_command_wr           <= 1'b0;
            
			ov_hcp_ext_command                 <= 66'b0;
			o_hcp_ext_command_wr               <= 1'b0;      
        end
    end
end    
endmodule
    